A Novel ANFIS Algorithm Architecture for FPGA Implementation

Darvill, John and Tisan, Alin and Cirstea, Marcian N. (2017) A Novel ANFIS Algorithm Architecture for FPGA Implementation. In: 2017 IEEE 26th International Symposium on Industrial Electronics (ISIE), 19-21 June 2017, Edinburgh, UK.

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Official URL: http://dx.doi.org/10.1109/ISIE.2017.8001423


This paper presents a new architecture for the Adaptive Neuro-Fuzzy Inference System (ANFIS) algorithm targeting FPGA implementation. This new architecture offers higher efficiency and scalability in comparison to the existing methods. The proposed architecture is modeled and simulated using VHDL and is targeted at a Xilinx FPGA. Existing implementation architectures are also modeled and comparisons are drawn between them in terms of both performance and logic utilization. The results show that the new architecture offers a reduction in calculation cycles of around 50% in comparison to the architecture from which it’s derived. This increase in calculation speed comes with only a modest increase in logic utilization, specifically a 2.5% increase in look-up table (LUT) usage and a 1.5% increase in flip-flop usage. The new architecture also eliminates scalability issues which can arise in the existing architectures when extra input members are required.

Item Type: Conference or Workshop Item (Paper)
Additional Information: © 2017 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.
Keywords: ANFIS algorithm, FPGA, VHDL
Faculty: ARCHIVED Faculty of Science & Technology (until September 2018)
Depositing User: Dr Alin Tisan
Date Deposited: 13 Jun 2017 14:57
Last Modified: 09 Sep 2021 18:58
URI: https://arro.anglia.ac.uk/id/eprint/701849

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