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A Novel ANFIS Algorithm Architecture for FPGA Implementation
conference contribution
posted on 2023-09-01, 14:06 authored by John Darvill, Alin Tisan, Marcian N. CirsteaThis paper presents a new architecture for the Adaptive Neuro-Fuzzy Inference System (ANFIS) algorithm targeting FPGA implementation. This new architecture offers higher efficiency and scalability in comparison to the existing methods. The proposed architecture is modeled and simulated using VHDL and is targeted at a Xilinx FPGA. Existing implementation architectures are also modeled and comparisons are drawn between them in terms of both performance and logic utilization. The results show that the new architecture offers a reduction in calculation cycles of around 50% in comparison to the architecture from which it’s derived. This increase in calculation speed comes with only a modest increase in logic utilization, specifically a 2.5% increase in look-up table (LUT) usage and a 1.5% increase in flip-flop usage. The new architecture also eliminates scalability issues which can arise in the existing architectures when extra input members are required.
History
ISSN
2163-5145External DOI
Publisher
IEEEPlace of publication
OnlineISBN
978-1-5090-1412-5Conference proceeding
2017 IEEE 26th International Symposium on Industrial Electronics (ISIE)Name of event
2017 IEEE 26th International Symposium on Industrial Electronics (ISIE)Location
Edinburgh, UKEvent start date
2017-06-19Event finish date
2017-06-21File version
- Other
Language
- eng
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Legacy posted date
2017-06-13Legacy creation date
2017-06-13Legacy Faculty/School/Department
ARCHIVED Faculty of Science & Technology (until September 2018)Note
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