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Direct neural-network hardware-implementation algorithm

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posted on 2023-08-30, 13:50 authored by Andrei Dinu, Marcian N. Cirstea, Silvia Cirstea
An algorithm for compact neural network hardware implementation is presented, which exploits special properties of the Boolean functions describing the operation of artificial neurones with step activation function. The algorithm contains three steps: ANN mathematical model digitisation, conversion of the digitised model into a logic gate structure, and hardware optimisation by elimination of redundant logic gates. A set of C++ programs automates algorithm implementation, generating optimised VHDL code. This strategy bridges the gap between ANN design software and hardware design packages (Xilinx). Although the method is directly applicable only to neurones with step activation functions, it can be extended to sigmoidal functions.

History

Refereed

  • Yes

Volume

57

Issue number

5

Page range

1845-1848

Publication title

IEEE Transactions on Industrial Electronics

ISSN

1557-9948

Publisher

IEEE

File version

  • Accepted version

Language

  • other

Legacy posted date

2013-07-18

Legacy creation date

2019-11-25

Legacy Faculty/School/Department

ARCHIVED Faculty of Science & Technology (until September 2018)

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