Direct neural-network hardware-implementation algorithm

Dinu, Andrei and Cirstea, Marcian N. and Cirstea, Silvia (2010) Direct neural-network hardware-implementation algorithm. IEEE Transactions on Industrial Electronics, 57 (5). pp. 1845-1848. ISSN 1557-9948

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Official URL: http://dx.doi.org/10.1109/TIE.2009.2033097

Abstract

An algorithm for compact neural network hardware implementation is presented, which exploits special properties of the Boolean functions describing the operation of artificial neurones with step activation function. The algorithm contains three steps: ANN mathematical model digitisation, conversion of the digitised model into a logic gate structure, and hardware optimisation by elimination of redundant logic gates. A set of C++ programs automates algorithm implementation, generating optimised VHDL code. This strategy bridges the gap between ANN design software and hardware design packages (Xilinx). Although the method is directly applicable only to neurones with step activation functions, it can be extended to sigmoidal functions.

Item Type: Journal Article
Keywords: Field-programmable gate array (FPGA), hardware implementation, neural networks
Faculty: ARCHIVED Faculty of Science & Technology (until September 2018)
Depositing User: Repository Admin
Date Deposited: 18 Jul 2013 12:46
Last Modified: 25 Nov 2019 15:46
URI: http://arro.anglia.ac.uk/id/eprint/296333

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