A Novel ANFIS Algorithm Architecture for FPGA Implementation

Darvill, John and Tisan, Alin and Cirstea, Marcian N. (2017) A Novel ANFIS Algorithm Architecture for FPGA Implementation. In: The 26th IEEE International Symposium on Industrial Electronics, 19-21 June 2017 Edinburgh, Scotland, UK, Edinburgh. (Accepted)

[img]
Preview
Text
Accepted Version
Available under the following license: Creative Commons Attribution Non-commercial No Derivatives.

Download (418kB) | Preview
[img] Text (Acceptance)
Other
Restricted to Repository staff only

Download (15kB)

Abstract

This paper presents a new architecture for the Adaptive Neuro-Fuzzy Inference System (ANFIS) algorithm targeting FPGA implementation. This new architecture offers higher efficiency and scalability in comparison to the existing methods. The proposed architecture is modeled and simulated using VHDL and is targeted at a Xilinx FPGA. Existing implementation architectures are also modeled and comparisons are drawn between them in terms of both performance and logic utilization. The results show that the new architecture offers a reduction in calculation cycles of around 50% in comparison to the architecture from which it’s derived. This increase in calculation speed comes with only a modest increase in logic utilization, specifically a 2.5% increase in look-up table (LUT) usage and a 1.5% increase in flip-flop usage. The new architecture also eliminates scalability issues which can arise in the existing architectures when extra input members are required.

Item Type: Conference or Workshop Item (Paper)
Keywords: ANFIS algorithm, FPGA, VHDL
Faculty: Faculty of Science & Technology
Depositing User: Dr Alin Tisan
Date Deposited: 13 Jun 2017 14:57
Last Modified: 13 Jun 2017 15:38
URI: http://arro.anglia.ac.uk/id/eprint/701849

Actions (login required)

Edit Item Edit Item