Simulink modeling and design of an efficient hardware-constrained FPGA-based PMSM speed controller

Alecsa, Bogdan and Cirstea, Marcian N. and Onea, Alexandru (2012) Simulink modeling and design of an efficient hardware-constrained FPGA-based PMSM speed controller. IEEE Transactions on Industrial Informatics. ISSN 1941-0050

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Abstract

The aim of this paper is to present a holistic approach to modeling and FPGA implementation of a permanent magnet synchronous motor (PMSM) speed controller. The whole system is modeled in the Matlab Simulink environment. The controller is then translated to discrete time and remodeled using System Generator blocks, directly synthesizable into FPGA hardware. The algorithm is further refined and factorized to take into account hardware constraints, so as to fit into a low cost FPGA, without significantly increasing the execution time. The resulting controller is then integrated together with sensor interfaces and analysis tools and implemented into an FPGA device. Experimental results validate the controller and verify the design.

Item Type: Journal Article
Additional Information: Citation: Alecsa, B., Cirstea, M.N. and Onea, A., 2012. Simulink modeling and design of an efficient hardware-constrained FPGA-based PMSM speed controller. IEEE Transactions on Industrial Informatics, 8(3), pp.554-562..
Faculty: Faculty of Science & Technology
Depositing User: Mr I Walker
Date Deposited: 18 Jul 2013 13:02
Last Modified: 30 Jun 2017 09:48
URI: http://arro.anglia.ac.uk/id/eprint/296349

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